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| author | Xiao Guangrong | 2014-04-17 11:06:15 +0200 |
|---|---|---|
| committer | Marcelo Tosatti | 2014-04-23 22:49:51 +0200 |
| commit | 7f31c9595e3c87f68dc54b3269e900f3017ed405 (patch) | |
| tree | 8545bf72ce7f938141a4f90c0b8c8fdb7c90c77f /arch/x86/kvm/mmu.c | |
| parent | KVM: MMU: lazily drop large spte (diff) | |
| download | kernel-qcow2-linux-7f31c9595e3c87f68dc54b3269e900f3017ed405.tar.gz kernel-qcow2-linux-7f31c9595e3c87f68dc54b3269e900f3017ed405.tar.xz kernel-qcow2-linux-7f31c9595e3c87f68dc54b3269e900f3017ed405.zip | |
KVM: MMU: flush tlb if the spte can be locklessly modified
Relax the tlb flush condition since we will write-protect the spte out of mmu
lock. Note lockless write-protection only marks the writable spte to readonly
and the spte can be writable only if both SPTE_HOST_WRITEABLE and
SPTE_MMU_WRITEABLE are set (that are tested by spte_is_locklessly_modifiable)
This patch is used to avoid this kind of race:
VCPU 0 VCPU 1
lockless wirte protection:
set spte.w = 0
lock mmu-lock
write protection the spte to sync shadow page,
see spte.w = 0, then without flush tlb
unlock mmu-lock
!!! At this point, the shadow page can still be
writable due to the corrupt tlb entry
Flush all TLB
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'arch/x86/kvm/mmu.c')
| -rw-r--r-- | arch/x86/kvm/mmu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index ddf06963a74c..388a2ef83911 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -595,7 +595,8 @@ static bool mmu_spte_update(u64 *sptep, u64 new_spte) * we always atomicly update it, see the comments in * spte_has_volatile_bits(). */ - if (is_writable_pte(old_spte) && !is_writable_pte(new_spte)) + if (spte_is_locklessly_modifiable(old_spte) && + !is_writable_pte(new_spte)) ret = true; if (!shadow_accessed_mask) |