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| author | Kuppuswamy Sathyanarayanan | 2013-12-16 21:07:37 +0100 |
|---|---|---|
| committer | H. Peter Anvin | 2014-01-15 23:38:58 +0100 |
| commit | 85611e3febe78955a519f5f9eb47b941525c8c76 (patch) | |
| tree | 86195f07a8e4afd24501a93c11b64c7122265d01 /arch/x86/platform/intel-mid/intel-mid.c | |
| parent | x86, intel-mid: Move Medfield code out of intel-mid.c core file (diff) | |
| download | kernel-qcow2-linux-85611e3febe78955a519f5f9eb47b941525c8c76.tar.gz kernel-qcow2-linux-85611e3febe78955a519f5f9eb47b941525c8c76.tar.xz kernel-qcow2-linux-85611e3febe78955a519f5f9eb47b941525c8c76.zip | |
x86, intel-mid: Add Clovertrail platform support
This patch adds Clovertrail support on intel-mid and makes it more
flexible to support other SoCs.
Signed-off-by: David Cohen <david.a.cohen@linux.intel.com>
Link: http://lkml.kernel.org/r/1387224459-25746-3-git-send-email-david.a.cohen@linux.intel.com
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/platform/intel-mid/intel-mid.c')
| -rw-r--r-- | arch/x86/platform/intel-mid/intel-mid.c | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c index 527d6d50643d..40955841bb32 100644 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -60,14 +60,27 @@ enum intel_mid_timer_options intel_mid_timer_options; +/* intel_mid_ops to store sub arch ops */ +struct intel_mid_ops *intel_mid_ops; +/* getter function for sub arch ops*/ +static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT; enum intel_mid_cpu_type __intel_mid_cpu_chip; EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); +static void intel_mid_power_off(void) +{ +}; + static void intel_mid_reboot(void) { intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); } +static unsigned long __init intel_mid_calibrate_tsc(void) +{ + return 0; +} + static void __init intel_mid_time_init(void) { sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); @@ -92,13 +105,33 @@ static void __init intel_mid_time_init(void) static void intel_mid_arch_setup(void) { - if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27) - __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; - else { + if (boot_cpu_data.x86 != 6) { pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", boot_cpu_data.x86, boot_cpu_data.x86_model); __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; + goto out; + } + + switch (boot_cpu_data.x86_model) { + case 0x35: + __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; + break; + case 0x27: + default: + __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; + break; } + + if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) + intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); + else { + intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); + pr_info("ARCH: Uknown SoC, assuming PENWELL!\n"); + } + +out: + if (intel_mid_ops->arch_setup) + intel_mid_ops->arch_setup(); } /* MID systems don't have i8042 controller */ |