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| author | Linus Torvalds | 2019-05-11 16:27:34 +0200 |
|---|---|---|
| committer | Linus Torvalds | 2019-05-11 16:27:34 +0200 |
| commit | 7a5575212ce4b6a41581b92fe03b6be1134793ba (patch) | |
| tree | f76ae29af196387330dd9a7c4a86200cbe80182c /arch/xtensa/include/asm/initialize_mmu.h | |
| parent | Merge tag 'docs-5.2a' of git://git.lwn.net/linux (diff) | |
| parent | xtensa: implement initialize_cacheattr for MPU cores (diff) | |
| download | kernel-qcow2-linux-7a5575212ce4b6a41581b92fe03b6be1134793ba.tar.gz kernel-qcow2-linux-7a5575212ce4b6a41581b92fe03b6be1134793ba.tar.xz kernel-qcow2-linux-7a5575212ce4b6a41581b92fe03b6be1134793ba.zip | |
Merge tag 'xtensa-20190510' of git://github.com/jcmvbkbc/linux-xtensa
Pull xtensa updates from Max Filippov:
- implement atomic operations using exclusive access Xtensa option
operations
- add support for Xtensa cores with memory protection unit (MPU)
- clean up xtensa-specific kernel-only headers
- fix error path in simdisk_setup
* tag 'xtensa-20190510' of git://github.com/jcmvbkbc/linux-xtensa:
xtensa: implement initialize_cacheattr for MPU cores
xtensa: add exclusive atomics support
xtensa: clean up inline assembly in futex.h
xtensa: replace variant/core.h with asm/core.h
xtensa: drop ifdef __KERNEL__ from kernel-only headers
xtensa: set proper error code for simdisk_setup()
xtensa: fix incorrect fd close in error case of simdisk_setup()
Diffstat (limited to 'arch/xtensa/include/asm/initialize_mmu.h')
| -rw-r--r-- | arch/xtensa/include/asm/initialize_mmu.h | 38 |
1 files changed, 33 insertions, 5 deletions
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h index 10e9852b2fb4..323d05789159 100644 --- a/arch/xtensa/include/asm/initialize_mmu.h +++ b/arch/xtensa/include/asm/initialize_mmu.h @@ -33,10 +33,6 @@ #define CA_WRITEBACK (0x4) #endif -#ifndef XCHAL_SPANNING_WAY -#define XCHAL_SPANNING_WAY 0 -#endif - #ifdef __ASSEMBLY__ #define XTENSA_HWVERSION_RC_2009_0 230000 @@ -181,11 +177,42 @@ .macro initialize_cacheattr -#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS +#if !defined(CONFIG_MMU) && (XCHAL_HAVE_TLBS || XCHAL_HAVE_MPU) #if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU #error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU. #endif +#if XCHAL_HAVE_MPU + .data + .align 4 +.Lattribute_table: + .long 0x000000, 0x1fff00, 0x1ddf00, 0x1eef00 + .long 0x006600, 0x000000, 0x000000, 0x000000 + .long 0x000000, 0x000000, 0x000000, 0x000000 + .long 0x000000, 0x000000, 0x000000, 0x000000 + .previous + + movi a3, .Lattribute_table + movi a4, CONFIG_MEMMAP_CACHEATTR + movi a5, 1 + movi a6, XCHAL_MPU_ENTRIES + movi a10, 0x20000000 + movi a11, -1 +1: + sub a5, a5, a10 + extui a8, a4, 28, 4 + beq a8, a11, 2f + addi a6, a6, -1 + mov a11, a8 +2: + addx4 a9, a8, a3 + l32i a9, a9, 0 + or a9, a9, a6 + wptlb a9, a5 + slli a4, a4, 4 + bgeu a5, a10, 1b + +#else movi a5, XCHAL_SPANNING_WAY movi a6, ~_PAGE_ATTRIB_MASK movi a4, CONFIG_MEMMAP_CACHEATTR @@ -208,6 +235,7 @@ isync #endif +#endif .endm |