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| author | Chris Zankel | 2014-08-19 02:30:24 +0200 |
|---|---|---|
| committer | Chris Zankel | 2014-08-19 02:30:24 +0200 |
| commit | e792290be763932d1b8cdf8a36d7015482a49d07 (patch) | |
| tree | 2aec72e1556ef099ff9bd535d21d4477e1db9ddb /arch/xtensa/include/asm/pgtable.h | |
| parent | Linux 3.17-rc1 (diff) | |
| parent | xtensa: deprecate fast_xtensa and fast_spill_registers syscalls (diff) | |
| download | kernel-qcow2-linux-e792290be763932d1b8cdf8a36d7015482a49d07.tar.gz kernel-qcow2-linux-e792290be763932d1b8cdf8a36d7015482a49d07.tar.xz kernel-qcow2-linux-e792290be763932d1b8cdf8a36d7015482a49d07.zip | |
Merge tag 'xtensa-for-next-20140815' into for_next
Xtensa improvements for 3.17:
- support highmem on cores with aliasing data cache. Enable highmem on kc705
by default;
- simplify addition of new core variants (no need to modify Kconfig /
Makefiles);
- improve robustness of unaligned access handler and its interaction with
window overflow/underflow exception handlers;
- deprecate atomic and spill registers syscalls;
- clean up Kconfig: remove orphan MATH_EMULATION, sort 'select' statements;
- wire up renameat2 syscall.
Various fixes:
- fix address checks in dma_{alloc,free}_coherent (runtime BUG);
- fix access to THREAD_RA/THREAD_SP/THREAD_DS (debug build breakage);
- fix TLBTEMP_BASE_2 region handling in fast_second_level_miss (runtime
unrecoverable exception);
- fix a6 and a7 handling in fast_syscall_xtensa (runtime userspace register
clobbering);
- fix kernel/user jump out of fast_unaligned (potential runtime unrecoverable
exception);
- replace termios IOCTL code definitions with constants (userspace build
breakage).
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/include/asm/pgtable.h')
| -rw-r--r-- | arch/xtensa/include/asm/pgtable.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h index 4b0ca35a93b1..b2173e5da601 100644 --- a/arch/xtensa/include/asm/pgtable.h +++ b/arch/xtensa/include/asm/pgtable.h @@ -67,7 +67,12 @@ #define VMALLOC_START 0xC0000000 #define VMALLOC_END 0xC7FEFFFF #define TLBTEMP_BASE_1 0xC7FF0000 -#define TLBTEMP_BASE_2 0xC7FF8000 +#define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE) +#if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE +#define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE) +#else +#define TLBTEMP_SIZE ICACHE_WAY_SIZE +#endif /* * For the Xtensa architecture, the PTE layout is as follows: |