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| author | Rajendra Nayak | 2009-07-25 03:44:01 +0200 |
|---|---|---|
| committer | paul | 2009-07-25 04:10:35 +0200 |
| commit | 8ff120e5303e27e03aba7b774e86fd43eaf90376 (patch) | |
| tree | 09d4487d784cf9656ea98615a7ebc8db52f25ef8 /arch | |
| parent | OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot (diff) | |
| download | kernel-qcow2-linux-8ff120e5303e27e03aba7b774e86fd43eaf90376.tar.gz kernel-qcow2-linux-8ff120e5303e27e03aba7b774e86fd43eaf90376.tar.xz kernel-qcow2-linux-8ff120e5303e27e03aba7b774e86fd43eaf90376.zip | |
OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83Mhz
This patch fixes a bug in the CORE dpll scaling sequence which was
errouneously clearing some bits in the SDRC DLLA CTRL register and
hence causing a freeze. The issue was observed only on platforms
which scale CORE dpll to < 83Mhz and hence program the DLL in fixed
delay mode.
Issue reported by Limei Wang <E12499@motorola.com>, with debugging
assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish
Ghongdemath <girishsg@ti.com>.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Limei Wang <E12499@motorola.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Girish Ghongdemath <girishsg@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: updated patch description to include collaboration credits]
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/sram34xx.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 9c2d0465a83c..e6b112590d7d 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -143,7 +143,7 @@ return_to_sdram: unlock_dll: ldr r11, omap3_sdrc_dlla_ctrl ldr r12, [r11] - and r12, r12, #FIXEDDELAY_MASK + bic r12, r12, #FIXEDDELAY_MASK orr r12, r12, #FIXEDDELAY_DEFAULT orr r12, r12, #DLLIDLE_MASK str r12, [r11] @ (no OCP barrier needed) |