summaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorMarek Vasut2012-07-09 18:22:53 +0200
committerWolfram Sang2012-07-13 10:33:42 +0200
commitcd4f2d4aa79ccbb2713f33f9c9f24ed21b5fc8fa (patch)
treef18425262e5ab482c4b6b12dbbf5ca8759ad33b3 /arch
parenti2c: i2c-bfin-twi: Move blackfin TWI register access Macro to head file. (diff)
downloadkernel-qcow2-linux-cd4f2d4aa79ccbb2713f33f9c9f24ed21b5fc8fa.tar.gz
kernel-qcow2-linux-cd4f2d4aa79ccbb2713f33f9c9f24ed21b5fc8fa.tar.xz
kernel-qcow2-linux-cd4f2d4aa79ccbb2713f33f9c9f24ed21b5fc8fa.zip
i2c: mxs: Set I2C timing registers for mxs-i2c
This patch configures the I2C bus timing registers according to information passed via DT. Currently, 100kHz and 400kHz modes are supported. The TIMING2 register value is wrong in the documentation for i.MX28! This was found and fixed by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx28.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 4634cb861a59..9af1606b5d3c 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -381,6 +381,7 @@
compatible = "fsl,imx28-i2c";
reg = <0x80058000 2000>;
interrupts = <111 68>;
+ clock-frequency = <100000>;
status = "disabled";
};
@@ -390,6 +391,7 @@
compatible = "fsl,imx28-i2c";
reg = <0x8005a000 2000>;
interrupts = <110 69>;
+ clock-frequency = <100000>;
status = "disabled";
};