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author | Tomi Valkeinen | 2009-01-28 03:44:31 +0100 |
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committer | Russell King | 2009-02-08 18:50:31 +0100 |
commit | 054ce503ae335dbc8610ef5aa0852c0c090023fe (patch) | |
tree | 31732b54d68aac75054b7a2affd0e1ccc369a43f /block/blk.h | |
parent | [ARM] OMAP3 powerdomains: remove RET from SGX power states list (diff) | |
download | kernel-qcow2-linux-054ce503ae335dbc8610ef5aa0852c0c090023fe.tar.gz kernel-qcow2-linux-054ce503ae335dbc8610ef5aa0852c0c090023fe.tar.xz kernel-qcow2-linux-054ce503ae335dbc8610ef5aa0852c0c090023fe.zip |
[ARM] OMAP: wait for pwrdm transition after clk_enable()
Enabling clock in a disabled power domain causes the power domain to be
turned on. However, the power transition is not always finished when
clk_enable() returns and this randomly crashes the kernel when an
interrupt happens right after the clk_enable, and the kernel tries to
read the irq status register for that domain.
Why the irq status register is inaccessible, I don't know. Also it
doesn't seem to be related to the module being not powered up, but to
the transition itself.
The same could perhaps happen after clk_disable also, but I have not
witnessed that.
The problem affects at least dss, cam and sgx clocks.
This change waits for the transition to be finished before returning
from omap2_clkdm_clk_enable().
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'block/blk.h')
0 files changed, 0 insertions, 0 deletions