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| author | Michal Simek | 2016-02-24 11:30:04 +0100 |
|---|---|---|
| committer | Michal Simek | 2017-06-22 15:37:00 +0200 |
| commit | 14ef905bb2eecb02f7ce31b8fbedd4a75ddf0f57 (patch) | |
| tree | b430bea7ffb54f04d7fb72ed6e1bd17b5d99c7a2 /block | |
| parent | microblaze: Separate GP registers from MSR handling (diff) | |
| download | kernel-qcow2-linux-14ef905bb2eecb02f7ce31b8fbedd4a75ddf0f57.tar.gz kernel-qcow2-linux-14ef905bb2eecb02f7ce31b8fbedd4a75ddf0f57.tar.xz kernel-qcow2-linux-14ef905bb2eecb02f7ce31b8fbedd4a75ddf0f57.zip | |
microblaze: Fix MSR flags when returning from exception
The issue was that the service routine was sometimes
returning with the wrong flags set in the MSR.
In this case, EIP bit was set while returning to User Mode
which is an illegal combination since exceptions are always
handled in privileged mode.
In order for MicroBlaze to take an interrupt, the MSR must have IE=1,
BIP=0 and EIP=0.
Signed-off-by: Stefan Asserhall <stefana@xilinx.com>
Signed-off-by: Goran Bilski <goran@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'block')
0 files changed, 0 insertions, 0 deletions