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authorPaulo Zanoni2013-01-25 19:59:11 +0100
committerDaniel Vetter2013-01-26 17:54:28 +0100
commitfa42e23c1055a4549c433ac56ff869e441c973c8 (patch)
treeb73dbd06e700e73a288d975618bf6f674e5b4874 /drivers/auxdisplay
parentdrm/i915: SWF screatch registers need an offset on VLV (diff)
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drm/i915: fix intel_init_power_wells
The current code was wrong in many different ways, so this is a full rewrite. We don't have "different power wells for different parts of the GPU", we have a single power well, but we have multiple registers that can be used to request enabling/disabling the power well. So let's be a good citizen and only use the register we're suppose to use, except when we're loading the driver, where we clear the request made by the BIOS. If any of the registers is requesting the power well to be enabled, it will be enabled. If none of the registers is requesting the power well to be enabled, it will be disabled. For now we're just forcing the power well to be enabled, but in the next commits we'll change this. V2: - Remove debug messages that could be misleading due to possible race conditions with KVMr, Debug and BIOS. - Don't wait on disabling: after a conversaion with a hardware engineer we discovered that the "restriction" on bit 31 is just for the "enable" case, and we don't even need to wait on the "disable" case. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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