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author | Martin Blumenstingl | 2017-04-01 15:02:25 +0200 |
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committer | Jerome Brunet | 2017-04-07 17:45:30 +0200 |
commit | b609338b26f5653aa211fc7af83477e2df6e3f0b (patch) | |
tree | 78dda6ea81fead69b83a6f39e5899f25f03b89ee /drivers/cdrom | |
parent | clk: meson: mpll: fix division by zero in rate_from_params (diff) | |
download | kernel-qcow2-linux-b609338b26f5653aa211fc7af83477e2df6e3f0b.tar.gz kernel-qcow2-linux-b609338b26f5653aa211fc7af83477e2df6e3f0b.tar.xz kernel-qcow2-linux-b609338b26f5653aa211fc7af83477e2df6e3f0b.zip |
clk: meson: mpll: use 64bit math in rate_from_params
On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz.
Multiplying this with SDM_DEN results in a value greater than 32bits.
This is not a problem on the 64bit Meson GX SoCs, but it may result in
undefined behavior on the older 32bit Meson8b SoC.
While rate_from_params was only introduced recently to make the math
reusable from _round_rate and _recalc_rate the original bug exists much
longer.
Fixes: 1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[as discussed on the ml, use DIV_ROUND_UP_ULL]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/cdrom')
0 files changed, 0 insertions, 0 deletions