[PATCH] snsc kmalloc2kzalloc - openslx/kernel-qcow2-linux.git

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author	Jes Sorensen	2006-03-23 12:00:49 +0100
committer	Linus Torvalds	2006-03-23 16:38:15 +0100
commit	40953ed87dd68742de0dd1bdecdcdfebfe1d69ae (patch)
tree	c5faa3efe1e3f8381d5d8674f068556abb9400d8 /drivers/char/snsc_event.c
parent	[PATCH] fat_lock is used as a mutex, convert it to using the new mutex primitive (diff)
download	kernel-qcow2-linux-40953ed87dd68742de0dd1bdecdcdfebfe1d69ae.tar.gz kernel-qcow2-linux-40953ed87dd68742de0dd1bdecdcdfebfe1d69ae.tar.xz kernel-qcow2-linux-40953ed87dd68742de0dd1bdecdcdfebfe1d69ae.zip

[PATCH] snsc kmalloc2kzalloc

Change driver to use kzalloc rather than kmalloc+memset Signed-off-by: Jes Sorensen <jes@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Diffstat (limited to 'drivers/char/snsc_event.c')

-rw-r--r--

drivers/char/snsc_event.c

1 files changed, 1 insertions, 4 deletions

// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2017 Chelsio Communications. All rights reserved. */ #include "t4_regs.h" #include "cxgb4.h" #include "cxgb4_cudbg.h" #include "cudbg_zlib.h" static const struct cxgb4_collect_entity cxgb4_collect_mem_dump[] = { { CUDBG_EDC0, cudbg_collect_edc0_meminfo }, { CUDBG_EDC1, cudbg_collect_edc1_meminfo }, { CUDBG_MC0, cudbg_collect_mc0_meminfo }, { CUDBG_MC1, cudbg_collect_mc1_meminfo }, { CUDBG_HMA, cudbg_collect_hma_meminfo }, }; static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = { { CUDBG_MBOX_LOG, cudbg_collect_mbox_log }, { CUDBG_QDESC, cudbg_collect_qdesc }, { CUDBG_DEV_LOG, cudbg_collect_fw_devlog }, { CUDBG_REG_DUMP, cudbg_collect_reg_dump }, { CUDBG_CIM_LA, cudbg_collect_cim_la }, { CUDBG_CIM_MA_LA, cudbg_collect_cim_ma_la }, { CUDBG_CIM_QCFG, cudbg_collect_cim_qcfg }, { CUDBG_CIM_IBQ_TP0, cudbg_collect_cim_ibq_tp0 }, { CUDBG_CIM_IBQ_TP1, cudbg_collect_cim_ibq_tp1 }, { CUDBG_CIM_IBQ_ULP, cudbg_collect_cim_ibq_ulp }, { CUDBG_CIM_IBQ_SGE0, cudbg_collect_cim_ibq_sge0 }, { CUDBG_CIM_IBQ_SGE1, cudbg_collect_cim_ibq_sge1 }, { CUDBG_CIM_IBQ_NCSI, cudbg_collect_cim_ibq_ncsi }, { CUDBG_CIM_OBQ_ULP0, cudbg_collect_cim_obq_ulp0 }, { CUDBG_CIM_OBQ_ULP1, cudbg_collect_cim_obq_ulp1 }, { CUDBG_CIM_OBQ_ULP2, cudbg_collect_cim_obq_ulp2 }, { CUDBG_CIM_OBQ_ULP3, cudbg_collect_cim_obq_ulp3 }, { CUDBG_CIM_OBQ_SGE, cudbg_collect_cim_obq_sge }, { CUDBG_CIM_OBQ_NCSI, cudbg_collect_cim_obq_ncsi }, { CUDBG_RSS, cudbg_collect_rss }, { CUDBG_RSS_VF_CONF, cudbg_collect_rss_vf_config }, { CUDBG_PATH_MTU, cudbg_collect_path_mtu }, { CUDBG_PM_STATS, cudbg_collect_pm_stats }, { CUDBG_HW_SCHED, cudbg_collect_hw_sched }, { CUDBG_TP_INDIRECT, cudbg_collect_tp_indirect }, { CUDBG_SGE_INDIRECT, cudbg_collect_sge_indirect }, { CUDBG_ULPRX_LA, cudbg_collect_ulprx_la }, { CUDBG_TP_LA, cudbg_collect_tp_la }, { CUDBG_MEMINFO, cudbg_collect_meminfo }, { CUDBG_CIM_PIF_LA, cudbg_collect_cim_pif_la }, { CUDBG_CLK, cudbg_collect_clk_info }, { CUDBG_CIM_OBQ_RXQ0, cudbg_collect_obq_sge_rx_q0 }, { CUDBG_CIM_OBQ_RXQ1, cudbg_collect_obq_sge_rx_q1 }, { CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect }, { CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect }, { CUDBG_TID_INFO, cudbg_collect_tid }, { CUDBG_PCIE_CONFIG, cudbg_collect_pcie_config }, { CUDBG_DUMP_CONTEXT, cudbg_collect_dump_context }, { CUDBG_MPS_TCAM, cudbg_collect_mps_tcam }, { CUDBG_VPD_DATA, cudbg_collect_vpd_data }, { CUDBG_LE_TCAM, cudbg_collect_le_tcam }, { CUDBG_CCTRL, cudbg_collect_cctrl }, { CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect }, { CUDBG_ULPTX_LA, cudbg_collect_ulptx_la }, { CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect }, { CUDBG_PBT_TABLE, cudbg_collect_pbt_tables }, { CUDBG_HMA_INDIRECT, cudbg_collect_hma_indirect }, }; static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity) { struct cudbg_tcam tcam_region = { 0 }; u32 value, n = 0, len = 0; switch (entity) { case CUDBG_REG_DUMP: switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { case CHELSIO_T4: len = T4_REGMAP_SIZE; break; case CHELSIO_T5: case CHELSIO_T6: len = T5_REGMAP_SIZE; break; default: break; } break; case CUDBG_DEV_LOG: len = adap->params.devlog.size; break; case CUDBG_CIM_LA: if (is_t6(adap->params.chip)) { len = adap->params.cim_la_size / 10 + 1; len *= 10 * sizeof(u32); } else { len = adap->params.cim_la_size / 8; len *= 8 * sizeof(u32); } len += sizeof(u32); /* for reading CIM LA configuration */ break; case CUDBG_CIM_MA_LA: len = 2 * CIM_MALA_SIZE * 5 * sizeof(u32); break; case CUDBG_CIM_QCFG: len = sizeof(struct cudbg_cim_qcfg); break; case CUDBG_CIM_IBQ_TP0: case CUDBG_CIM_IBQ_TP1: case CUDBG_CIM_IBQ_ULP: case CUDBG_CIM_IBQ_SGE0: case CUDBG_CIM_IBQ_SGE1: case CUDBG_CIM_IBQ_NCSI: len = CIM_IBQ_SIZE * 4 * sizeof(u32); break; case CUDBG_CIM_OBQ_ULP0: len = cudbg_cim_obq_size(adap, 0); break; case CUDBG_CIM_OBQ_ULP1: len = cudbg_cim_obq_size(adap, 1); break; case CUDBG_CIM_OBQ_ULP2: len = cudbg_cim_obq_size(adap, 2); break; case CUDBG_CIM_OBQ_ULP3: len = cudbg_cim_obq_size(adap, 3); break; case CUDBG_CIM_OBQ_SGE: len = cudbg_cim_obq_size(adap, 4); break; case CUDBG_CIM_OBQ_NCSI: len = cudbg_cim_obq_size(adap, 5); break; case CUDBG_CIM_OBQ_RXQ0: len = cudbg_cim_obq_size(adap, 6); break; case CUDBG_CIM_OBQ_RXQ1: len = cudbg_cim_obq_size(adap, 7); break; case CUDBG_EDC0: value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); if (value & EDRAM0_ENABLE_F) { value = t4_read_reg(adap, MA_EDRAM0_BAR_A); len = EDRAM0_SIZE_G(value); } len = cudbg_mbytes_to_bytes(len); break; case CUDBG_EDC1: value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); if (value & EDRAM1_ENABLE_F) { value = t4_read_reg(adap, MA_EDRAM1_BAR_A); len = EDRAM1_SIZE_G(value); } len = cudbg_mbytes_to_bytes(len); break; case CUDBG_MC0: value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); if (value & EXT_MEM0_ENABLE_F) { value = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); len = EXT_MEM0_SIZE_G(value); } len = cudbg_mbytes_to_bytes(len); break; case CUDBG_MC1: value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A); if (value & EXT_MEM1_ENABLE_F) { value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); len = EXT_MEM1_SIZE_G(value); } len = cudbg_mbytes_to_bytes(len); break; case CUDBG_RSS: len = t4_chip_rss_size(adap) * sizeof(u16); break; case CUDBG_RSS_VF_CONF: len = adap->params.arch.vfcount * sizeof(struct cudbg_rss_vf_conf); break; case CUDBG_PATH_MTU: len = NMTUS * sizeof(u16); break; case CUDBG_PM_STATS: len = sizeof(struct cudbg_pm_stats); break; case CUDBG_HW_SCHED: len = sizeof(struct cudbg_hw_sched); break; case CUDBG_TP_INDIRECT: switch (CHELSIO_CHIP_VERSION(adap->params.chip)) { case CHELSIO_T5: n = sizeof(t5_tp_pio_array) + sizeof(t5_tp_tm_pio_array) + sizeof(t5_tp_mib_index_array); break; case CHELSIO_T6: n = sizeof(t6_tp_pio_array) + sizeof(t6_tp_tm_pio_array) + sizeof(t6_tp_mib_index_array); break; default: break; } n = n / (IREG_NUM_ELEM * sizeof(u32)); len = sizeof(struct ireg_buf) * n; break; case CUDBG_SGE_INDIRECT: len = sizeof(struct ireg_buf) * 2 + sizeof(struct sge_qbase_reg_field); break; case CUDBG_ULPRX_LA: len = sizeof(struct cudbg_ulprx_la); break; case CUDBG_TP_LA: len = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64); break; case CUDBG_MEMINFO: len = sizeof(struct cudbg_ver_hdr) + sizeof(struct cudbg_meminfo); break; case CUDBG_CIM_PIF_LA: len = sizeof(struct cudbg_cim_pif_la); len += 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32); break; case CUDBG_CLK: len = sizeof(struct cudbg_clk_info); break; case CUDBG_PCIE_INDIRECT: n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32)); len = sizeof(struct ireg_buf) * n * 2; break; case CUDBG_PM_INDIRECT: n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32)); len = sizeof(struct ireg_buf) * n * 2; break; case CUDBG_TID_INFO: len = sizeof(struct cudbg_tid_info_region_rev1); break; case CUDBG_PCIE_CONFIG: len = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS; break; case CUDBG_DUMP_CONTEXT: len = cudbg_dump_context_size(adap); break; case CUDBG_MPS_TCAM: len = sizeof(struct cudbg_mps_tcam) * adap->params.arch.mps_tcam_size; break; case CUDBG_VPD_DATA: len = sizeof(struct cudbg_vpd_data); break; case CUDBG_LE_TCAM: cudbg_fill_le_tcam_info(adap, &tcam_region); len = sizeof(struct cudbg_tcam) + sizeof(struct cudbg_tid_data) * tcam_region.max_tid; break; case CUDBG_CCTRL: len = sizeof(u16) * NMTUS * NCCTRL_WIN; break; case CUDBG_MA_INDIRECT: if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); len = sizeof(struct ireg_buf) * n * 2; } break; case CUDBG_ULPTX_LA: len = sizeof(struct cudbg_ver_hdr) + sizeof(struct cudbg_ulptx_la); break; case CUDBG_UP_CIM_INDIRECT: n = 0; if (is_t5(adap->params.chip)) n = sizeof(t5_up_cim_reg_array) / ((IREG_NUM_ELEM + 1) * sizeof(u32)); else if (is_t6(adap->params.chip)) n = sizeof(t6_up_cim_reg_array) / ((IREG_NUM_ELEM + 1) * sizeof(u32)); len = sizeof(struct ireg_buf) * n; break; case CUDBG_PBT_TABLE: len = sizeof(struct cudbg_pbt_tables); break; case CUDBG_MBOX_LOG: len = sizeof(struct cudbg_mbox_log) * adap->mbox_log->size; break; case CUDBG_HMA_INDIRECT: if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32)); len = sizeof(struct ireg_buf) * n; } break; case CUDBG_HMA:


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