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| author | Zhenyu Wang | 2010-11-02 10:30:46 +0100 |
|---|---|---|
| committer | Chris Wilson | 2010-11-02 11:05:46 +0100 |
| commit | d110852513148a7ec44fad4e036455aeb816d713 (patch) | |
| tree | 5c72fa12fa653804a4d13658a641a713d6849acd /drivers/char | |
| parent | Revert "drm/i915: add MMIO debug output" (diff) | |
| download | kernel-qcow2-linux-d110852513148a7ec44fad4e036455aeb816d713.tar.gz kernel-qcow2-linux-d110852513148a7ec44fad4e036455aeb816d713.tar.xz kernel-qcow2-linux-d110852513148a7ec44fad4e036455aeb816d713.zip | |
agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char')
| -rw-r--r-- | drivers/char/agp/intel-gtt.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index f800e9cfc368..c51efe6f2c7f 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -1291,11 +1291,11 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, if (type_mask == AGP_USER_UNCACHED_MEMORY) pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { - pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; + pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; if (gfdt) pte_flags |= GEN6_PTE_GFDT; } else { /* set 'normal'/'cached' to LLC by default */ - pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; + pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; if (gfdt) pte_flags |= GEN6_PTE_GFDT; } |