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| author | Stephen Boyd | 2017-06-17 00:01:46 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2017-06-17 00:01:46 +0200 |
| commit | 4dea04c1f113a848cec8722d2401127227623820 (patch) | |
| tree | 6339770db64cc56c1b6370f560fa03fe79749130 /drivers/clk/hisilicon/clk-hi3660.c | |
| parent | Merge branch 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm in... (diff) | |
| parent | clk: meson: gxbb: add all clk81 parents (diff) | |
| download | kernel-qcow2-linux-4dea04c1f113a848cec8722d2401127227623820.tar.gz kernel-qcow2-linux-4dea04c1f113a848cec8722d2401127227623820.tar.xz kernel-qcow2-linux-4dea04c1f113a848cec8722d2401127227623820.zip | |
Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next
Pull Amlogic clk driver updates from Jerome Brunet:
* Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
* Add new compatible to the meson8 clock controller for meson8b
* Add missing parents to gxbb clk81
* tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson:
clk: meson: gxbb: add all clk81 parents
clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
clk: meson8b: export the ethernet gate clock
clk: meson8b: export the USB clocks
clk: meson8b: export the gate clock for the HW random number generator
clk: meson8b: export the SDIO clock
clk: meson8b: export the SAR ADC clocks
Diffstat (limited to 'drivers/clk/hisilicon/clk-hi3660.c')
0 files changed, 0 insertions, 0 deletions