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| author | Zhong Kaihua | 2017-08-07 16:51:56 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2017-11-14 18:48:59 +0100 |
| commit | d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8 (patch) | |
| tree | 3cbf8228d5ff1de69e50ed66726e281e0ecabb86 /drivers/clk/hisilicon/clkgate-separated.c | |
| parent | clk: hi6220: mark clock cs_atb_syspll as critical (diff) | |
| download | kernel-qcow2-linux-d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8.tar.gz kernel-qcow2-linux-d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8.tar.xz kernel-qcow2-linux-d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8.zip | |
clk: hi3660: fix incorrect uart3 clock freqency
UART3 clock rate is doubled in previous commit.
This error is not detected until recently a mezzanine board which makes
real use of uart3 port (through LS connector of 96boards) was setup
and tested on hi3660-hikey960 board.
This patch changes clock source rate of clk_factor_uart3 to 100000000.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/hisilicon/clkgate-separated.c')
0 files changed, 0 insertions, 0 deletions