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| author | Harvey Hunt | 2016-05-09 18:29:52 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2016-05-12 23:48:25 +0200 |
| commit | 4afe2d1a6ed5cba794aeeaa816e7c97a45167b01 (patch) | |
| tree | e88fd50b5e791760c7abb20f01e087c53583fe34 /drivers/clk/ingenic/jz4740-cgu.c | |
| parent | Merge tag 'v4.7-rockchip-clk4' of git://git.kernel.org/pub/scm/linux/kernel/g... (diff) | |
| download | kernel-qcow2-linux-4afe2d1a6ed5cba794aeeaa816e7c97a45167b01.tar.gz kernel-qcow2-linux-4afe2d1a6ed5cba794aeeaa816e7c97a45167b01.tar.xz kernel-qcow2-linux-4afe2d1a6ed5cba794aeeaa816e7c97a45167b01.zip | |
clk: ingenic: Allow divider value to be divided
The JZ4780's MSC clock divider registers multiply the clock divider by 2.
This means that MMC devices run at half their expected speed. Add the
ability to divide the clock divider in order to solve this.
Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/ingenic/jz4740-cgu.c')
| -rw-r--r-- | drivers/clk/ingenic/jz4740-cgu.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 305a26c2a800..510fe7e0c8f1 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -90,51 +90,51 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_PLL_HALF] = { "pll half", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, - .div = { CGU_REG_CPCCR, 21, 1, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 }, }, [JZ4740_CLK_CCLK] = { "cclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, - .div = { CGU_REG_CPCCR, 0, 4, 22, -1, -1 }, + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, }, [JZ4740_CLK_HCLK] = { "hclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, - .div = { CGU_REG_CPCCR, 4, 4, 22, -1, -1 }, + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, [JZ4740_CLK_PCLK] = { "pclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, - .div = { CGU_REG_CPCCR, 8, 4, 22, -1, -1 }, + .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 }, }, [JZ4740_CLK_MCLK] = { "mclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, - .div = { CGU_REG_CPCCR, 12, 4, 22, -1, -1 }, + .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 }, }, [JZ4740_CLK_LCD] = { "lcd", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, - .div = { CGU_REG_CPCCR, 16, 5, 22, -1, -1 }, + .div = { CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1 }, .gate = { CGU_REG_CLKGR, 10 }, }, [JZ4740_CLK_LCD_PCLK] = { "lcd_pclk", CGU_CLK_DIV, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, - .div = { CGU_REG_LPCDR, 0, 11, -1, -1, -1 }, + .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, }, [JZ4740_CLK_I2S] = { "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 31, 1 }, - .div = { CGU_REG_I2SCDR, 0, 8, -1, -1, -1 }, + .div = { CGU_REG_I2SCDR, 0, 1, 8, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 6 }, }, @@ -142,21 +142,21 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 }, .mux = { CGU_REG_SSICDR, 31, 1 }, - .div = { CGU_REG_SSICDR, 0, 4, -1, -1, -1 }, + .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 4 }, }, [JZ4740_CLK_MMC] = { "mmc", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, - .div = { CGU_REG_MSCCDR, 0, 5, -1, -1, -1 }, + .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 7 }, }, [JZ4740_CLK_UHC] = { "uhc", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 }, - .div = { CGU_REG_UHCCDR, 0, 4, -1, -1, -1 }, + .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, .gate = { CGU_REG_CLKGR, 14 }, }, @@ -164,7 +164,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { "udc", CGU_CLK_MUX | CGU_CLK_DIV, .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 }, .mux = { CGU_REG_CPCCR, 29, 1 }, - .div = { CGU_REG_CPCCR, 23, 6, -1, -1, -1 }, + .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, .gate = { CGU_REG_SCR, 6 }, }, |