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| author | Ondrej Jirman | 2016-11-25 01:28:47 +0100 |
|---|---|---|
| committer | Maxime Ripard | 2017-01-02 22:24:55 +0100 |
| commit | a43c96427e713bea94e9ef50e8be1f493afc0691 (patch) | |
| tree | 64d672ed9bd3c1e371b29d323eceb51aa9f870f4 /drivers/clk/mediatek | |
| parent | Linux 4.10-rc1 (diff) | |
| download | kernel-qcow2-linux-a43c96427e713bea94e9ef50e8be1f493afc0691.tar.gz kernel-qcow2-linux-a43c96427e713bea94e9ef50e8be1f493afc0691.tar.xz kernel-qcow2-linux-a43c96427e713bea94e9ef50e8be1f493afc0691.zip | |
clk: sunxi-ng: fix PLL_CPUX adjusting on H3
When adjusting PLL_CPUX on H3, the PLL is temporarily driven
too high, and the system becomes unstable (oopses or hangs).
Add a notifier to avoid this situation by temporarily switching
to a known stable 24 MHz oscillator.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Tested-by: Lutz Sammer <johns98@gmx.net>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions