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| author | Jerome Brunet | 2017-07-28 18:32:28 +0200 |
|---|---|---|
| committer | Neil Armstrong | 2017-08-01 14:18:31 +0200 |
| commit | 1f737ffa13efd3da2c703d45894ea234e9290c89 (patch) | |
| tree | c7b8e973a1121f26b9f4f0f53277fac73ca5273c /drivers/clk/meson/clk-mpll.c | |
| parent | Linux v4.13-rc1 (diff) | |
| download | kernel-qcow2-linux-1f737ffa13efd3da2c703d45894ea234e9290c89.tar.gz kernel-qcow2-linux-1f737ffa13efd3da2c703d45894ea234e9290c89.tar.xz kernel-qcow2-linux-1f737ffa13efd3da2c703d45894ea234e9290c89.zip | |
clk: meson: mpll: fix mpll0 fractional part ignored
mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider
Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clk-mpll.c')
| -rw-r--r-- | drivers/clk/meson/clk-mpll.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index 39eab69fe51a..44a5a535ca63 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw, reg = PARM_SET(p->width, p->shift, reg, 1); writel(reg, mpll->base + p->reg_off); + p = &mpll->ssen; + if (p->width != 0) { + reg = readl(mpll->base + p->reg_off); + reg = PARM_SET(p->width, p->shift, reg, 1); + writel(reg, mpll->base + p->reg_off); + } + p = &mpll->n2; reg = readl(mpll->base + p->reg_off); reg = PARM_SET(p->width, p->shift, reg, n2); |