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author | Martin Blumenstingl | 2018-05-20 19:16:06 +0200 |
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committer | Jerome Brunet | 2018-05-21 10:33:58 +0200 |
commit | 72e1f2302040398dafb64bbb93abdde78c1f2267 (patch) | |
tree | ffcbf6278eba0c4f8a59a829292205d17a07527a /drivers/clk/meson/clk-mpll.c | |
parent | clk: meson: use SPDX license identifiers consistently (diff) | |
download | kernel-qcow2-linux-72e1f2302040398dafb64bbb93abdde78c1f2267.tar.gz kernel-qcow2-linux-72e1f2302040398dafb64bbb93abdde78c1f2267.tar.xz kernel-qcow2-linux-72e1f2302040398dafb64bbb93abdde78c1f2267.zip |
clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL
Until commit 05f814402d6174 ("clk: meson: add fdiv clock gates") we
relied on the bootloader to enable the fclk_div clock gates. It turns
out that our clock tree is incomplete at least on Meson8b (tested with
an Odroid-C1, which uses an RGMII PHY) because after the mentioned
commit Ethernet is not working anymore (no RX/TX activity can be seen).
At the same time Ethernet was still working on Meson8m2 with a RMII PHY.
Testing has shown that as soon as "fclk_div2" is disabled Ethernet stops
working on Odroid-C1. Unfortunately it's currently not clear what the
Ethernet controller IP block uses the fclk_div2 clock for. Mark the
clock as CLK_IS_CRITICAL to keep it enabled (as it's already enabled by
most bootloaders by default, which is why we didn't notice it before).
Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates")
Cc: stable@vger.kernel.org
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clk-mpll.c')
0 files changed, 0 insertions, 0 deletions