diff options
| author | Jerome Brunet | 2017-03-09 11:41:50 +0100 |
|---|---|---|
| committer | Michael Turquette | 2017-03-27 21:30:18 +0200 |
| commit | 007e6e5c5f01d379da91e0e30f83245022fd2579 (patch) | |
| tree | ba18d708147c3dadee0abb42fd83d07d09b89478 /drivers/clk/meson/clkc.h | |
| parent | clk: gxbb: put dividers and muxes in tables (diff) | |
| download | kernel-qcow2-linux-007e6e5c5f01d379da91e0e30f83245022fd2579.tar.gz kernel-qcow2-linux-007e6e5c5f01d379da91e0e30f83245022fd2579.tar.xz kernel-qcow2-linux-007e6e5c5f01d379da91e0e30f83245022fd2579.zip | |
clk: meson: mpll: add rw operation
This patch adds new callbacks to the meson-mpll driver to control
and set the pll rate. For this, we also need to add the enable bit and
sdm enable bit. The corresponding parameters are added to mpll data
structure.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-6-jbrunet@baylibre.com
Diffstat (limited to 'drivers/clk/meson/clkc.h')
| -rw-r--r-- | drivers/clk/meson/clkc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index c6be77dd8694..ad254675edd8 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -92,8 +92,9 @@ struct meson_clk_mpll { struct clk_hw hw; void __iomem *base; struct parm sdm; + struct parm sdm_en; struct parm n2; - /* FIXME ssen gate control? */ + struct parm en; spinlock_t *lock; }; @@ -116,5 +117,6 @@ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; extern const struct clk_ops meson_clk_cpu_ops; extern const struct clk_ops meson_clk_mpll_ro_ops; +extern const struct clk_ops meson_clk_mpll_ops; #endif /* __CLKC_H */ |