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| author | Michael Turquette | 2016-06-07 03:08:15 +0200 |
|---|---|---|
| committer | Michael Turquette | 2016-06-23 03:05:47 +0200 |
| commit | 4a47295144ddbcf802fcddb3d7c0736d9a1f2e40 (patch) | |
| tree | e988e9fddbcae63d64496b086d9be5c81e2bbc21 /drivers/clk/meson/clkc.h | |
| parent | clk: meson: add mpll support (diff) | |
| download | kernel-qcow2-linux-4a47295144ddbcf802fcddb3d7c0736d9a1f2e40.tar.gz kernel-qcow2-linux-4a47295144ddbcf802fcddb3d7c0736d9a1f2e40.tar.xz kernel-qcow2-linux-4a47295144ddbcf802fcddb3d7c0736d9a1f2e40.zip | |
clk: meson: fractional pll support
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add
in a couple of new bitfields for further dividing the clock rate to
achieve rates with fractional hertz.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clkc.h')
| -rw-r--r-- | drivers/clk/meson/clkc.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 73f014691240..53326c32e853 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -40,7 +40,10 @@ struct pll_rate_table { u16 m; u16 n; u16 od; + u16 od2; + u16 frac; }; + #define PLL_RATE(_r, _m, _n, _od) \ { \ .rate = (_r), \ @@ -49,12 +52,24 @@ struct pll_rate_table { .od = (_od), \ } \ +#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \ + { \ + .rate = (_r), \ + .m = (_m), \ + .n = (_n), \ + .od = (_od), \ + .od2 = (_od2), \ + .frac = (_frac), \ + } \ + struct meson_clk_pll { struct clk_hw hw; void __iomem *base; struct parm m; struct parm n; + struct parm frac; struct parm od; + struct parm od2; const struct pll_rate_table *rate_table; unsigned int rate_count; spinlock_t *lock; |