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| author | Neil Armstrong | 2018-11-06 15:57:34 +0100 |
|---|---|---|
| committer | Neil Armstrong | 2018-11-23 15:11:56 +0100 |
| commit | 72dbb8c94d0d8a44d1a006fd487e755e2de48dec (patch) | |
| tree | 7e3bb995ee0532c09ac00feb9527b7890cad0f02 /drivers/clk/meson/clkc.h | |
| parent | dt-bindings: clock: meson8b: export the CPU post dividers (diff) | |
| download | kernel-qcow2-linux-72dbb8c94d0d8a44d1a006fd487e755e2de48dec.tar.gz kernel-qcow2-linux-72dbb8c94d0d8a44d1a006fd487e755e2de48dec.tar.xz kernel-qcow2-linux-72dbb8c94d0d8a44d1a006fd487e755e2de48dec.zip | |
clk: meson: Add vid_pll divider driver
Add support the VID_PLL fully programmable divider used right after the
HDMI PLL clock source. It is used to achieve complex fractional division
with a programmble bitfield.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: http://lkml.kernel.org/r/1541516257-16157-2-git-send-email-narmstrong@baylibre.com
Diffstat (limited to 'drivers/clk/meson/clkc.h')
| -rw-r--r-- | drivers/clk/meson/clkc.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 6b96d55c047d..91666055c75a 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -90,6 +90,11 @@ struct meson_clk_phase_data { int meson_clk_degrees_from_val(unsigned int val, unsigned int width); unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width); +struct meson_vid_pll_div_data { + struct parm val; + struct parm sel; +}; + #define MESON_GATE(_name, _reg, _bit) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ @@ -112,5 +117,6 @@ extern const struct clk_ops meson_clk_cpu_ops; extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_phase_ops; +extern const struct clk_ops meson_vid_pll_div_ro_ops; #endif /* __CLKC_H */ |