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| author | Jerome Brunet | 2018-02-19 12:21:39 +0100 |
|---|---|---|
| committer | Neil Armstrong | 2018-03-13 10:09:45 +0100 |
| commit | 8289aafa4f361050b05f77a35d3167259530a473 (patch) | |
| tree | 13a2fdfe6ff4ae6abcecf06f2de989b62c2d74f8 /drivers/clk/meson/clkc.h | |
| parent | clk: meson: remove special gp0 lock loop (diff) | |
| download | kernel-qcow2-linux-8289aafa4f361050b05f77a35d3167259530a473.tar.gz kernel-qcow2-linux-8289aafa4f361050b05f77a35d3167259530a473.tar.xz kernel-qcow2-linux-8289aafa4f361050b05f77a35d3167259530a473.zip | |
clk: meson: improve pll driver results with frac
Finding the appropriate settings of meson plls is too tricky to be done
entirely at runtime, using calculation only. Many combination of m, n
and od won't lock which is why we are using a table for this. However,
for plls having a fractional parameters, it is possible to improve on
the result provided by the table by calculating the frac parameter.
This change adds the calculation of frac when the parameter is available
and the rate provided by the table is not an exact match for the
requested rate.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/clkc.h')
| -rw-r--r-- | drivers/clk/meson/clkc.h | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index ebd88afe1eb5..9cdcd9b6c16c 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -61,7 +61,6 @@ struct pll_rate_table { u16 od; u16 od2; u16 od3; - u16 frac; }; #define PLL_RATE(_r, _m, _n, _od) \ @@ -70,17 +69,7 @@ struct pll_rate_table { .m = (_m), \ .n = (_n), \ .od = (_od), \ - } \ - -#define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \ - { \ - .rate = (_r), \ - .m = (_m), \ - .n = (_n), \ - .od = (_od), \ - .od2 = (_od2), \ - .frac = (_frac), \ - } \ + } struct meson_clk_pll_data { struct parm m; |