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| author | Jerome Brunet | 2018-02-19 12:21:45 +0100 |
|---|---|---|
| committer | Neil Armstrong | 2018-03-13 10:09:58 +0100 |
| commit | 05f814402d6174369b3b29832cbb5eb5ed287059 (patch) | |
| tree | 55806276dd6ea4734e2ec86238680c4e4ec06961 /drivers/clk/meson/gxbb.h | |
| parent | clk: meson: add mpll pre-divider (diff) | |
| download | kernel-qcow2-linux-05f814402d6174369b3b29832cbb5eb5ed287059.tar.gz kernel-qcow2-linux-05f814402d6174369b3b29832cbb5eb5ed287059.tar.xz kernel-qcow2-linux-05f814402d6174369b3b29832cbb5eb5ed287059.zip | |
clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate
independently. We never had an issue so far because these clocks
were provided 'enabled' by the bootloader.
Add these gates to enable/disable the clocks when required.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb.h')
| -rw-r--r-- | drivers/clk/meson/gxbb.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index afae007ae1ec..9febf3f03739 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -199,8 +199,13 @@ #define CLKID_MPLL1_DIV 143 #define CLKID_MPLL2_DIV 144 #define CLKID_MPLL_PREDIV 145 +#define CLKID_FCLK_DIV2_DIV 146 +#define CLKID_FCLK_DIV3_DIV 147 +#define CLKID_FCLK_DIV4_DIV 148 +#define CLKID_FCLK_DIV5_DIV 149 +#define CLKID_FCLK_DIV7_DIV 150 -#define NR_CLKS 146 +#define NR_CLKS 151 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/gxbb-clkc.h> |