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| author | Neil Armstrong | 2017-03-22 11:32:25 +0100 |
|---|---|---|
| committer | Kevin Hilman | 2017-04-04 21:05:14 +0200 |
| commit | 0d48fc558d01ded71ffad3fe6cca8081847ac9a7 (patch) | |
| tree | c46ffb1692c940c1c280e158c1046b26de69ae49 /drivers/clk/meson/gxbb.h | |
| parent | clk: meson-gxbb: Add GP0 PLL init parameters (diff) | |
| download | kernel-qcow2-linux-0d48fc558d01ded71ffad3fe6cca8081847ac9a7.tar.gz kernel-qcow2-linux-0d48fc558d01ded71ffad3fe6cca8081847ac9a7.tar.xz kernel-qcow2-linux-0d48fc558d01ded71ffad3fe6cca8081847ac9a7.zip | |
clk: meson-gxbb: Add GXL/GXM GP0 Variant
The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM
SoCs embeds a different GP0 PLL, and needs different parameters with a vendor
provided reduced rate table.
This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order
to use the GXL GP0 PLL instead of the GXBB specific one.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1490178747-14837-4-git-send-email-narmstrong@baylibre.com
Diffstat (limited to 'drivers/clk/meson/gxbb.h')
| -rw-r--r-- | drivers/clk/meson/gxbb.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 8ee2022ce5d5..7f99bf6ca10c 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -71,6 +71,8 @@ #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ +#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ +#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ |