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| author | Gregory CLEMENT | 2016-09-30 10:33:59 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2016-10-18 00:35:10 +0200 |
| commit | 4aa6c99d31c0cc471b7f243f5d314391a1abcaf3 (patch) | |
| tree | b2bf9c4c519e0ff4ba28e75863b760391f2427f1 /drivers/clk/mvebu | |
| parent | clk: bcm2835: Clamp the PLL's requested rate to the hardware limits. (diff) | |
| download | kernel-qcow2-linux-4aa6c99d31c0cc471b7f243f5d314391a1abcaf3.tar.gz kernel-qcow2-linux-4aa6c99d31c0cc471b7f243f5d314391a1abcaf3.tar.xz kernel-qcow2-linux-4aa6c99d31c0cc471b7f243f5d314391a1abcaf3.zip | |
clk: mvebu: armada-37xx-periph: Fix the clock gate flag
For the gate part of the peripheral clock setting the bit disables the
clock and clearing it enables the clock. This is not the default behavior
of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mvebu')
| -rw-r--r-- | drivers/clk/mvebu/armada-37xx-periph.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index d5dfbad4ceab..cecb0fdfaef6 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -329,6 +329,7 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data, gate->lock = lock; gate_ops = gate_hw->init->ops; gate->reg = reg + (u64)gate->reg; + gate->flags = CLK_GATE_SET_TO_DISABLE; } if (data->rate_hw) { |