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| author | Stephen Boyd | 2018-08-14 14:12:21 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2018-10-17 22:14:37 +0200 |
| commit | b3f2f10693aadeacf83ab5be03810941a4b77612 (patch) | |
| tree | db313603ce51128df1956cf836693bc2c13ca626 /drivers/clk/qcom/clk-hfpll.h | |
| parent | ARM: Add Krait L2 register accessor functions (diff) | |
| download | kernel-qcow2-linux-b3f2f10693aadeacf83ab5be03810941a4b77612.tar.gz kernel-qcow2-linux-b3f2f10693aadeacf83ab5be03810941a4b77612.tar.xz kernel-qcow2-linux-b3f2f10693aadeacf83ab5be03810941a4b77612.zip | |
clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
HFPLLs are the main frequency source for Krait CPU clocks. Add
support for changing the rate of these PLLs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Tested-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/clk-hfpll.h')
| -rw-r--r-- | drivers/clk/qcom/clk-hfpll.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-hfpll.h b/drivers/clk/qcom/clk-hfpll.h new file mode 100644 index 000000000000..2a57b2fb2f2f --- /dev/null +++ b/drivers/clk/qcom/clk-hfpll.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __QCOM_CLK_HFPLL_H__ +#define __QCOM_CLK_HFPLL_H__ + +#include <linux/clk-provider.h> +#include <linux/spinlock.h> +#include "clk-regmap.h" + +struct hfpll_data { + u32 mode_reg; + u32 l_reg; + u32 m_reg; + u32 n_reg; + u32 user_reg; + u32 droop_reg; + u32 config_reg; + u32 status_reg; + u8 lock_bit; + + u32 droop_val; + u32 config_val; + u32 user_val; + u32 user_vco_mask; + unsigned long low_vco_max_rate; + + unsigned long min_rate; + unsigned long max_rate; +}; + +struct clk_hfpll { + struct hfpll_data const *d; + int init_done; + + struct clk_regmap clkr; + spinlock_t lock; +}; + +#define to_clk_hfpll(_hw) \ + container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr) + +extern const struct clk_ops clk_ops_hfpll; + +#endif |