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| author | Stephen Boyd | 2014-04-29 00:59:16 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2014-09-23 00:16:54 +0200 |
| commit | 229fd4a505553c3a475b90e9aa8e452f5d78eb3b (patch) | |
| tree | 5f4b5b22574558f9d41e93f3d9f01f7290695cb2 /drivers/clk/qcom/clk-rcg.h | |
| parent | clk: qcom: Add support for setting rates on PLLs (diff) | |
| download | kernel-qcow2-linux-229fd4a505553c3a475b90e9aa8e452f5d78eb3b.tar.gz kernel-qcow2-linux-229fd4a505553c3a475b90e9aa8e452f5d78eb3b.tar.xz kernel-qcow2-linux-229fd4a505553c3a475b90e9aa8e452f5d78eb3b.zip | |
clk: qcom: Add support for banked MD RCGs
The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-rcg.h')
| -rw-r--r-- | drivers/clk/qcom/clk-rcg.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index ba0523cefd2e..687e41f91d7c 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -103,8 +103,9 @@ extern const struct clk_ops clk_rcg_bypass_ops; * struct clk_dyn_rcg - root clock generator with glitch free mux * * @mux_sel_bit: bit to switch glitch free mux - * @ns_reg: NS register + * @ns_reg: NS0 and NS1 register * @md_reg: MD0 and MD1 register + * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux * @mn: mn counter (banked) * @s: source selector (banked) * @freq_tbl: frequency table @@ -113,8 +114,9 @@ extern const struct clk_ops clk_rcg_bypass_ops; * */ struct clk_dyn_rcg { - u32 ns_reg; + u32 ns_reg[2]; u32 md_reg[2]; + u32 bank_reg; u8 mux_sel_bit; |