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authorStephen Boyd2016-03-02 02:26:48 +0100
committerStephen Boyd2016-03-02 23:31:31 +0100
commit0f75e1a370fd843c9e508fc1ccf0662833034827 (patch)
treec73d8de4cf553398140082990185ebd8d81eab57 /drivers/clk/qcom/gcc-msm8960.c
parentMerge branch 'clk-ti' into clk-next (diff)
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clk: qcom: msm8960: Fix ce3_src register offset
The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/gcc-msm8960.c')
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 63ecd97f3793..0a0c1f533249 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2753,7 +2753,7 @@ static struct clk_rcg ce3_src = {
},
.freq_tbl = clk_tbl_ce3,
.clkr = {
- .enable_reg = 0x2c08,
+ .enable_reg = 0x36c0,
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "ce3_src",