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| author | Gareth Williams | 2019-03-22 12:33:04 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven | 2019-04-02 09:50:48 +0200 |
| commit | 1addd6d568d02a9a1ce44307ec9c678e66e18c9e (patch) | |
| tree | ecec6dd7e0a00ed7b20f901eb9b096269798f10d /drivers/clk/renesas | |
| parent | clk: renesas: r7s9210: Always use readl() (diff) | |
| download | kernel-qcow2-linux-1addd6d568d02a9a1ce44307ec9c678e66e18c9e.tar.gz kernel-qcow2-linux-1addd6d568d02a9a1ce44307ec9c678e66e18c9e.tar.xz kernel-qcow2-linux-1addd6d568d02a9a1ce44307ec9c678e66e18c9e.zip | |
clk: renesas: r9a06g032: Add missing PCI USB clock
The clock driver is missing support for the clk_pci_usb clock that is
present on the SoC. This is added to allow the clock to be supported.
Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r9a06g032-clocks.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 658cb11b6f55..97c72477cd54 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -170,6 +170,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] __initconst = { D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0), D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0), D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0), + D_GATE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0), D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0), D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0), D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0), |