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| author | Heiko Stuebner | 2014-11-20 20:38:52 +0100 |
|---|---|---|
| committer | Heiko Stuebner | 2014-11-25 09:57:18 +0100 |
| commit | 0bb66d3b6e78168f8f49c7a41060508707f04d1d (patch) | |
| tree | 812b8a0face8604c03d472bbb75b7066b092687e /drivers/clk/rockchip/clk-rk3288.c | |
| parent | clk: rockchip: setup pll_mux data earlier (diff) | |
| download | kernel-qcow2-linux-0bb66d3b6e78168f8f49c7a41060508707f04d1d.tar.gz kernel-qcow2-linux-0bb66d3b6e78168f8f49c7a41060508707f04d1d.tar.xz kernel-qcow2-linux-0bb66d3b6e78168f8f49c7a41060508707f04d1d.zip | |
clk: rockchip: add optional sync to pll rate parameters
In some cases firmware brings up plls with different parameters than the ones
noted in the rate table for the specific frequency. These firmware-selected
parameters are worse than the tested ones in the pll rate tables but cannot
be changed by a simple clk_set_rate call when the rate stays the same.
Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback
that checks the runtime-parameters against the matching rate table entry
and adjusts them to the table-ones if necessary.
If no rate table is set or the current rate does not match any rate-table
entry no changes are made.
Being able to limit this adjustment to specific plls is necessary to not
touch the ones supplying core components like the apll and dpll supplying
the armcores and dram.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3288.c')
0 files changed, 0 insertions, 0 deletions