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| author | Lin Huang | 2016-08-22 05:36:17 +0200 |
|---|---|---|
| committer | Heiko Stuebner | 2016-09-01 11:23:56 +0200 |
| commit | a4f182bf81f18f91f1aef6289fcdfa6a2ac51b99 (patch) | |
| tree | 36c23cf0b8be22260303e345259c426e209326ac /drivers/clk/rockchip/clk.c | |
| parent | Merge branch 'v4.9-shared/sip-hdr' into v4.9-clk/next (diff) | |
| download | kernel-qcow2-linux-a4f182bf81f18f91f1aef6289fcdfa6a2ac51b99.tar.gz kernel-qcow2-linux-a4f182bf81f18f91f1aef6289fcdfa6a2ac51b99.tar.xz kernel-qcow2-linux-a4f182bf81f18f91f1aef6289fcdfa6a2ac51b99.zip | |
clk: rockchip: add new clock-type for the ddrclk
Changing the rate of the DDR clock needs special care, as the DDR
is of course in use and will react badly if the rate changes under it.
Over time different approaches to handle that were used.
Past SoCs like the rk3288 and before would store some code in SRAM
while the rk3368 used a SCPI variant and let a coprocessor handle that.
New rockchip platforms like the rk3399 have a dcf controller to do ddr
frequency scaling, and support for this controller will be implemented
in the arm-trusted-firmware.
This new clock-type should over time handle all these methods for
handling DDR rate changes, but right now it will concentrate on the
SIP interface used to talk to ARM trusted firmware.
The SIP interface counterpart was merged from pull-request #684 [0]
into the upstream arm-trusted-firmware codebase.
[0] https://github.com/ARM-software/arm-trusted-firmware/pull/684
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
| -rw-r--r-- | drivers/clk/rockchip/clk.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 1f1c74f3744b..b886be30f34f 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -484,6 +484,15 @@ void __init rockchip_clk_register_branches( list->gate_offset, list->gate_shift, list->gate_flags, flags, &ctx->lock); break; + case branch_ddrclk: + clk = rockchip_clk_register_ddrclk( + list->name, list->flags, + list->parent_names, list->num_parents, + list->muxdiv_offset, list->mux_shift, + list->mux_width, list->div_shift, + list->div_width, list->div_flags, + ctx->reg_base, &ctx->lock); + break; } /* none of the cases above matched */ |