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| author | Marek Szyprowski | 2018-03-06 15:33:09 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki | 2018-03-06 17:39:16 +0100 |
| commit | ec4016ff6e60fffab2e34fe87578c6362147cb98 (patch) | |
| tree | 4574de4d8afc60c5765bfc48e43484a06f4f06a2 /drivers/clk/samsung/clk-exynos5-subcmu.c | |
| parent | clk: samsung: Add Exynos5 sub-CMU clock driver (diff) | |
| download | kernel-qcow2-linux-ec4016ff6e60fffab2e34fe87578c6362147cb98.tar.gz kernel-qcow2-linux-ec4016ff6e60fffab2e34fe87578c6362147cb98.tar.xz kernel-qcow2-linux-ec4016ff6e60fffab2e34fe87578c6362147cb98.zip | |
clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU
Clocks related to DISP, GSC and MFC blocks require special handling for
power domain turn on/off sequences. Till now this was handled by Exynos
power domain driver, but that approach was limited only to some special
cases. This patch moves handling of those operations to clock controller
driver. This gives more flexibility and allows fine tune values of some
clock-specific registers. This patch moves handling of those mentioned
clocks to Exynos5 sub-CMU driver instantiated from Exynos5420 driver.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5-subcmu.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5-subcmu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c index ac3983c8adf2..bea10f4b3ee2 100644 --- a/drivers/clk/samsung/clk-exynos5-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -165,6 +165,8 @@ static int __init exynos5_clk_probe(struct platform_device *pdev) } static const struct of_device_id exynos5_clk_of_match[] = { + { .compatible = "samsung,exynos5420-clock", }, + { .compatible = "samsung,exynos5800-clock", }, { }, }; |