diff options
| author | Tomasz Figa | 2013-10-15 19:41:19 +0200 |
|---|---|---|
| committer | Tomasz Figa | 2013-12-30 18:15:48 +0100 |
| commit | 256dd646a30fb7bc6720b636e8b9098cd492e603 (patch) | |
| tree | 2d6283636c7c44f25248abb28e127949e4d00901 /drivers/clk/samsung/clk-exynos5250.c | |
| parent | clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain (diff) | |
| download | kernel-qcow2-linux-256dd646a30fb7bc6720b636e8b9098cd492e603.tar.gz kernel-qcow2-linux-256dd646a30fb7bc6720b636e8b9098cd492e603.tar.xz kernel-qcow2-linux-256dd646a30fb7bc6720b636e8b9098cd492e603.zip | |
clk: samsung: exynos5250: Add missing unpopulated mux parents
This patch updates mux parent arrays with unpopulated mux inputs, as all
inputs need to be specified in parent arrays passed to
clk_register_mux(), otherwise clk_set_parent() can generate out of bound
accesses to the array.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5250.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index d29faabd2150..73334b8d9f66 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -204,19 +204,27 @@ PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", "mout_mpll_user", "mout_epll", "mout_vpll", - "mout_cpll" }; + "mout_cpll", "none", "none", + "none", "none", "none", + "none" }; PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", "mout_mpll_user", "mout_epll", "mout_vpll", - "mout_cpll" }; + "mout_cpll", "none", "none", + "none", "none", "none", + "none" }; PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", "mout_mpll_user", "mout_epll", "mout_vpll", - "mout_cpll" }; + "mout_cpll", "none", "none", + "none", "none", "none", + "none" }; PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", "mout_mpll_user", "mout_epll", "mout_vpll", - "mout_cpll" }; + "mout_cpll", "none", "none", + "none", "none", "none", + "none" }; PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", "spdif_extclk" }; |