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author | Linus Torvalds | 2019-08-20 01:28:25 +0200 |
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committer | Linus Torvalds | 2019-08-20 01:28:25 +0200 |
commit | 5f97cbe22b7616ead7ae267c29cad73bc1444811 (patch) | |
tree | 6c390d8bd5bd95616d73b2185417499fe0cfcbe8 /drivers/clk/samsung/clk-exynos5250.c | |
parent | Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git... (diff) | |
parent | clk: Fix potential NULL dereference in clk_fetch_parent_index() (diff) | |
download | kernel-qcow2-linux-5f97cbe22b7616ead7ae267c29cad73bc1444811.tar.gz kernel-qcow2-linux-5f97cbe22b7616ead7ae267c29cad73bc1444811.tar.xz kernel-qcow2-linux-5f97cbe22b7616ead7ae267c29cad73bc1444811.zip |
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A couple fixes to the core framework logic that finds clk parents, a
handful of samsung clk driver fixes for audio and display clks, and a
small fix for the Stratix10 SoC driver that was checking the wrong
register for validity"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: Fix potential NULL dereference in clk_fetch_parent_index()
clk: Fix falling back to legacy parent string matching
clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
clk: samsung: exynos542x: Move MSCL subsystem clocks to its sub-CMU
clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMU
clk: samsung: Change signature of exynos5_subcmus_init() function
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5250.c')
-rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index f2b896881768..931c70a4da19 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -681,6 +681,10 @@ static const struct exynos5_subcmu_info exynos5250_disp_subcmu = { .pd_name = "DISP1", }; +static const struct exynos5_subcmu_info *exynos5250_subcmus[] = { + &exynos5250_disp_subcmu, +}; + static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -843,7 +847,8 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_sleep_init(reg_base, exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs)); - exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu); + exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus), + exynos5250_subcmus); samsung_clk_of_add_provider(np, ctx); |