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authorRahul Sharma2013-08-23 09:16:59 +0200
committerMike Turquette2013-08-29 04:23:40 +0200
commite2815b048aa05bc2e1c0a49ffd23ebed47e9c813 (patch)
tree30b43f6f56062e70e2e1029cef8ca42320f75db8 /drivers/clk/samsung/clk-exynos5250.c
parentclk: tegra30: Don't wait for PLL_U lock bit (diff)
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clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem
parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5250.c')
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index a9916a46e7a7..d90e59326252 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -489,8 +489,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
- GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
- GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
+ GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
+ GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
};