diff options
| author | Sachin Kamat | 2014-03-13 04:27:02 +0100 |
|---|---|---|
| committer | Tomasz Figa | 2014-05-14 19:23:37 +0200 |
| commit | 53cb6342dee87c99c61bc4d9f3dd4471936f71e7 (patch) | |
| tree | 15db12c190e8140174058dee9004d27025369880 /drivers/clk/samsung/clk-exynos5420.c | |
| parent | clk: samsung: exynos5250/5420: Add gate clock for SSS module (diff) | |
| download | kernel-qcow2-linux-53cb6342dee87c99c61bc4d9f3dd4471936f71e7.tar.gz kernel-qcow2-linux-53cb6342dee87c99c61bc4d9f3dd4471936f71e7.tar.xz kernel-qcow2-linux-53cb6342dee87c99c61bc4d9f3dd4471936f71e7.zip | |
clk: samsung: exynos5420: Fix VPLL lock offset
Set it as per the user manual.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5420.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index a8704540a214..676a0bdabba0 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -34,7 +34,7 @@ #define RPLL_LOCK 0x10050 #define IPLL_LOCK 0x10060 #define SPLL_LOCK 0x10070 -#define VPLL_LOCK 0x10070 +#define VPLL_LOCK 0x10080 #define MPLL_LOCK 0x10090 #define CPLL_CON0 0x10120 #define DPLL_CON0 0x10128 |