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| author | Dinh Nguyen | 2015-05-20 05:22:41 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2015-05-22 00:10:38 +0200 |
| commit | 5611a5ba8e5435740df99235b262b553f687b13b (patch) | |
| tree | a89f45daaed9443cfa48176f9319baeae2cb9e0d /drivers/clk/socfpga/clk-gate.c | |
| parent | clk: clk-conf: Fix typo in comment (diff) | |
| download | kernel-qcow2-linux-5611a5ba8e5435740df99235b262b553f687b13b.tar.gz kernel-qcow2-linux-5611a5ba8e5435740df99235b262b553f687b13b.tar.xz kernel-qcow2-linux-5611a5ba8e5435740df99235b262b553f687b13b.zip | |
clk: socfpga: update clk.h so for Arria10 platform to use
There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define
SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver
can use.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-gate.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-gate.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 0d5dc84372dc..0add360525a0 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -32,14 +32,10 @@ #define SOCFPGA_MMC_CLK "sdmmc_clk" #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 -#define streq(a, b) (strcmp((a), (b)) == 0) - #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) /* SDMMC Group for System Manager defines */ #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) { |