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| author | Sylwester Nawrocki | 2019-08-08 16:49:29 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2019-08-08 22:53:58 +0200 |
| commit | b6adeb6bc61c2567b9efd815d61a61b34a2e51a6 (patch) | |
| tree | d2bce5cde8959ef6273a1dd6bf902bd1a2496b0d /drivers/clk/socfpga/clk-periph-s10.c | |
| parent | clk: samsung: Change signature of exynos5_subcmus_init() function (diff) | |
| download | kernel-qcow2-linux-b6adeb6bc61c2567b9efd815d61a61b34a2e51a6.tar.gz kernel-qcow2-linux-b6adeb6bc61c2567b9efd815d61a61b34a2e51a6.tar.xz kernel-qcow2-linux-b6adeb6bc61c2567b9efd815d61a61b34a2e51a6.zip | |
clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMU
This patch fixes broken sound on Exynos5422/5800 platforms after
system/suspend resume cycle in cases where the audio root clock
is derived from MAU_EPLL_CLK.
In order to preserve state of the USER_MUX_MAU_EPLL_CLK clock mux
during system suspend/resume cycle for Exynos5800 we group the MAU
block input clocks in "MAU" sub-CMU and add the clock mux control
bit to .suspend_regs. This ensures that user configuration of the mux
is not lost after the PMU block changes the mux setting to OSC_DIV
when switching off the MAU power domain.
Adding the SRC_TOP9 register to exynos5800_clk_regs[] array is not
sufficient as at the time of the syscore_ops suspend call MAU power
domain is already turned off and we already save and subsequently
restore an incorrect register's value.
Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Reported-by: Jaafar Ali <jaafarkhalaf@gmail.com>
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Jaafar Ali <jaafarkhalaf@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lkml.kernel.org/r/20190808144929.18685-2-s.nawrocki@samsung.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-periph-s10.c')
0 files changed, 0 insertions, 0 deletions