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author | Jernej Skrabec | 2018-08-09 18:52:13 +0200 |
---|---|---|
committer | Maxime Ripard | 2018-08-27 09:18:01 +0200 |
commit | cb54fbd21a8fd97c2a82a069e8c80abdedbeb530 (patch) | |
tree | 90a2ebc3f6afe2e5b550b65765b8b8cb1adfa5b2 /drivers/clk/sunxi-ng/ccu_nm.c | |
parent | clk: sunxi-ng: h6: fix PWM gate/reset offset (diff) | |
download | kernel-qcow2-linux-cb54fbd21a8fd97c2a82a069e8c80abdedbeb530.tar.gz kernel-qcow2-linux-cb54fbd21a8fd97c2a82a069e8c80abdedbeb530.tar.xz kernel-qcow2-linux-cb54fbd21a8fd97c2a82a069e8c80abdedbeb530.zip |
clk: sunxi-ng: Add maximum rate constraint to NM PLLs
On some NM PLLs, frequency can be set above PLL working range.
Add a constraint for maximum supported rate. This way, drivers can
specify which is maximum allowed rate for PLL.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_nm.c')
-rw-r--r-- | drivers/clk/sunxi-ng/ccu_nm.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c index 4e2073307f34..6fe3c14f7b2d 100644 --- a/drivers/clk/sunxi-ng/ccu_nm.c +++ b/drivers/clk/sunxi-ng/ccu_nm.c @@ -124,6 +124,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate, return rate; } + if (nm->max_rate && rate > nm->max_rate) { + rate = nm->max_rate; + if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) + rate /= nm->fixed_post_div; + return rate; + } + if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) rate /= nm->fixed_post_div; |