diff options
| author | Bill Huang | 2015-06-18 23:28:26 +0200 |
|---|---|---|
| committer | Thierry Reding | 2015-11-20 18:05:04 +0100 |
| commit | fde207eb15115f1081e589267ebdf442aa54cda5 (patch) | |
| tree | d6f9907076138f33db9691e28d8b6bcfded1a214 /drivers/clk/tegra/clk-pll.c | |
| parent | clk: tegra: pll: Add logic for out-of-table rates for T210 (diff) | |
| download | kernel-qcow2-linux-fde207eb15115f1081e589267ebdf442aa54cda5.tar.gz kernel-qcow2-linux-fde207eb15115f1081e589267ebdf442aa54cda5.tar.xz kernel-qcow2-linux-fde207eb15115f1081e589267ebdf442aa54cda5.zip | |
clk: tegra: pll: Add code to handle if resets are supported by PLL
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index fb3e3f67586c..c645a899deba 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -311,6 +311,12 @@ static void _clk_pll_enable(struct clk_hw *hw) udelay(2); } + if (pll->params->reset_reg) { + val = pll_readl(pll->params->reset_reg, pll); + val &= ~BIT(pll->params->reset_bit_idx); + pll_writel(val, pll->params->reset_reg, pll); + } + clk_pll_enable_lock(pll); val = pll_readl_base(pll); @@ -343,6 +349,12 @@ static void _clk_pll_disable(struct clk_hw *hw) writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); } + if (pll->params->reset_reg) { + val = pll_readl(pll->params->reset_reg, pll); + val |= BIT(pll->params->reset_bit_idx); + pll_writel(val, pll->params->reset_reg, pll); + } + if (pll->params->iddq_reg) { val = pll_readl(pll->params->iddq_reg, pll); val |= BIT(pll->params->iddq_bit_idx); |