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| author | Mark Zhang | 2013-12-27 01:44:24 +0100 |
|---|---|---|
| committer | Peter De Schrijver | 2014-02-17 15:18:16 +0100 |
| commit | 82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874 (patch) | |
| tree | 0c9a829ca83489a35631d43e3f124bfcd35eb7d5 /drivers/clk/tegra/clk-tegra124.c | |
| parent | clk: tegra: PLLD2 fixes for hdmi (diff) | |
| download | kernel-qcow2-linux-82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874.tar.gz kernel-qcow2-linux-82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874.tar.xz kernel-qcow2-linux-82ba1c3c9988a8055f4a4d7ca2168e9efe7e7874.zip | |
clk: tegra: fix host1x clock on Tegra124
The host1x clock on Tegra124 is a 3-bit wide mux with 6 parents.
Change thte id to tegra_clk_host1x_8 so that the correct clock gets
registered.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra124.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 0fc912691789..743ccb4c3507 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -775,7 +775,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true }, [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true }, [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true }, - [tegra_clk_host1x] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true }, + [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true }, [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true }, [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true }, [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true }, |