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| author | Thierry Reding | 2014-04-04 15:55:15 +0200 |
|---|---|---|
| committer | Peter De Schrijver | 2014-04-17 13:12:46 +0200 |
| commit | 4ccc402ece35695dd2884ec0b652d52ae0230f13 (patch) | |
| tree | e72273317bd892e4678ee6ccf776831e863554a1 /drivers/clk/tegra | |
| parent | clk: tegra: Introduce divider mask and shift helpers (diff) | |
| download | kernel-qcow2-linux-4ccc402ece35695dd2884ec0b652d52ae0230f13.tar.gz kernel-qcow2-linux-4ccc402ece35695dd2884ec0b652d52ae0230f13.tar.xz kernel-qcow2-linux-4ccc402ece35695dd2884ec0b652d52ae0230f13.zip | |
clk: tegra: Fix enabling of PLLE
When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 1187187a1cf2..7a1b70dac824 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -757,7 +757,7 @@ static int clk_plle_enable(struct clk_hw *hw) val |= PLLE_SS_DISABLE; writel(val, pll->clk_base + PLLE_SS_CTRL); - val |= pll_readl_base(pll); + val = pll_readl_base(pll); val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); pll_writel_base(val, pll); |