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| author | Masahiro Yamada | 2016-12-07 02:32:33 +0100 |
|---|---|---|
| committer | Stephen Boyd | 2016-12-08 01:17:03 +0100 |
| commit | 1221ae211f64207f5caf40f9a03f9b8e50ff80cc (patch) | |
| tree | 401676bfc3f584abf3582994ba9f03379484c813 /drivers/clk/uniphier/clk-uniphier.h | |
| parent | clk: uniphier: add CPU-gear change (cpufreq) support (diff) | |
| download | kernel-qcow2-linux-1221ae211f64207f5caf40f9a03f9b8e50ff80cc.tar.gz kernel-qcow2-linux-1221ae211f64207f5caf40f9a03f9b8e50ff80cc.tar.xz kernel-qcow2-linux-1221ae211f64207f5caf40f9a03f9b8e50ff80cc.zip | |
clk: uniphier: add cpufreq data for LD11, LD20 SoCs
Add more data to 64bit SoCs for the cpufreq support.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/uniphier/clk-uniphier.h')
| -rw-r--r-- | drivers/clk/uniphier/clk-uniphier.h | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 9707b0fbe733..01c16ecec48f 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -75,6 +75,20 @@ struct uniphier_clk_data { } data; }; +#define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask, \ + _num_parents, ...) \ + { \ + .name = (_name), \ + .type = UNIPHIER_CLK_TYPE_CPUGEAR, \ + .idx = (_idx), \ + .data.cpugear = { \ + .parent_names = { __VA_ARGS__ }, \ + .num_parents = (_num_parents), \ + .regbase = (_regbase), \ + .mask = (_mask) \ + }, \ + } + #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \ { \ .name = (_name), \ @@ -87,7 +101,6 @@ struct uniphier_clk_data { }, \ } - #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ { \ .name = (_name), \ @@ -100,6 +113,21 @@ struct uniphier_clk_data { }, \ } +#define UNIPHIER_CLK_DIV(parent, div) \ + UNIPHIER_CLK_FACTOR(parent "/" #div, -1, parent, 1, div) + +#define UNIPHIER_CLK_DIV2(parent, div0, div1) \ + UNIPHIER_CLK_DIV(parent, div0), \ + UNIPHIER_CLK_DIV(parent, div1) + +#define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ + UNIPHIER_CLK_DIV2(parent, div0, div1), \ + UNIPHIER_CLK_DIV(parent, div2) + +#define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ + UNIPHIER_CLK_DIV2(parent, div0, div1), \ + UNIPHIER_CLK_DIV2(parent, div2, div3) + struct clk_hw *uniphier_clk_register_cpugear(struct device *dev, struct regmap *regmap, const char *name, |