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| author | Shawn Guo | 2017-03-21 09:38:21 +0100 |
|---|---|---|
| committer | Michael Turquette | 2017-04-12 18:51:29 +0200 |
| commit | 5790d801762c588c63b41fbdbdb8295cfd6036e6 (patch) | |
| tree | a10c8e3f63c2d2b96f83cace96496b095ac1cae1 /drivers/clk/zte/clk.c | |
| parent | clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock (diff) | |
| download | kernel-qcow2-linux-5790d801762c588c63b41fbdbdb8295cfd6036e6.tar.gz kernel-qcow2-linux-5790d801762c588c63b41fbdbdb8295cfd6036e6.tar.xz kernel-qcow2-linux-5790d801762c588c63b41fbdbdb8295cfd6036e6.zip | |
clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.
While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/zte/clk.c')
0 files changed, 0 insertions, 0 deletions