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authorEmilio López2014-03-19 19:19:32 +0100
committerMike Turquette2014-03-19 20:34:56 +0100
commit2226013972da1ec0a2aeb13a684180bb2b50e0f3 (patch)
tree46eb6fa45466430ff9995979607226d4c18f2e87 /drivers/clk
parentclk: sunxi: fix A20 PLL4 calculation (diff)
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clk: sunxi: fix some calculations
Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index ef6ad52b7546..aaec9d7867d0 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -299,7 +299,7 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
if (parent_rate < *freq)
*freq = parent_rate;
- parent_rate = (parent_rate + (*freq - 1)) / *freq;
+ parent_rate = DIV_ROUND_UP(parent_rate, *freq);
/* Invalid rate! */
if (parent_rate > 32)
@@ -344,7 +344,7 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
if (*freq > parent_rate)
*freq = parent_rate;
- div = parent_rate / *freq;
+ div = DIV_ROUND_UP(parent_rate, *freq);
if (div < 16)
calcp = 0;
@@ -385,7 +385,7 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
if (*freq > parent_rate)
*freq = parent_rate;
- div = parent_rate / *freq;
+ div = DIV_ROUND_UP(parent_rate, *freq);
if (div < 32)
calcp = 0;