diff options
| author | Tomoya MORINAGA | 2011-07-21 02:19:58 +0200 |
|---|---|---|
| committer | Grant Likely | 2011-10-05 19:59:17 +0200 |
| commit | e98bed7f0fa847492db8316db4605f2681f39868 (patch) | |
| tree | 4f284ab6b290b870b9ddebb25b09ece26fa22c02 /drivers/gpio/gpio-pch.c | |
| parent | gpio-pch: modify gpio_nums and mask (diff) | |
| download | kernel-qcow2-linux-e98bed7f0fa847492db8316db4605f2681f39868.tar.gz kernel-qcow2-linux-e98bed7f0fa847492db8316db4605f2681f39868.tar.xz kernel-qcow2-linux-e98bed7f0fa847492db8316db4605f2681f39868.zip | |
gpio-pch: Save register value in suspend()
Currently, when suspend is occurred, register im0/1 and gpio_use_sel are not
saved.
This patch modifies so that register im0/1 and gpio_use_sel are saved.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/gpio/gpio-pch.c')
| -rw-r--r-- | drivers/gpio/gpio-pch.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-pch.c b/drivers/gpio/gpio-pch.c index 4ac69bd7ad4a..7f773afeb340 100644 --- a/drivers/gpio/gpio-pch.c +++ b/drivers/gpio/gpio-pch.c @@ -30,7 +30,8 @@ struct pch_regs { u32 pm; u32 im0; u32 im1; - u32 reserved[4]; + u32 reserved[3]; + u32 gpio_use_sel; u32 reset; }; @@ -51,10 +52,17 @@ static int gpio_pins[] = { * struct pch_gpio_reg_data - The register store data. * @po_reg: To store contents of PO register. * @pm_reg: To store contents of PM register. + * @im0_reg: To store contents of IM0 register. + * @im1_reg: To store contents of IM1 register. + * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register. + * (Only ML7223 Bus-n) */ struct pch_gpio_reg_data { u32 po_reg; u32 pm_reg; + u32 im0_reg; + u32 im1_reg; + u32 gpio_use_sel_reg; }; /** @@ -149,6 +157,12 @@ static void pch_gpio_save_reg_conf(struct pch_gpio *chip) { chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); + chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); + if (chip->ioh == INTEL_EG20T_PCH) + chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); + if (chip->ioh == OKISEMI_ML7223n_IOH) + chip->pch_gpio_reg.gpio_use_sel_reg =\ + ioread32(&chip->reg->gpio_use_sel); } /* @@ -160,6 +174,12 @@ static void pch_gpio_restore_reg_conf(struct pch_gpio *chip) iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); /* to store contents of PM register */ iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); + iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); + if (chip->ioh == INTEL_EG20T_PCH) + iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); + if (chip->ioh == OKISEMI_ML7223n_IOH) + iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, + &chip->reg->gpio_use_sel); } static void pch_gpio_setup(struct pch_gpio *chip) |