diff options
| author | Monk Liu | 2016-11-02 08:33:46 +0100 |
|---|---|---|
| committer | Alex Deucher | 2017-03-30 05:54:57 +0200 |
| commit | 3fc08b61df3837701fd6665c1b2b3df7ca44225b (patch) | |
| tree | 10169252a2d48744dfaba34e302a125de471bcbb /drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | |
| parent | drm/amdgpu: add Vega10 Device IDs (v2) (diff) | |
| download | kernel-qcow2-linux-3fc08b61df3837701fd6665c1b2b3df7ca44225b.tar.gz kernel-qcow2-linux-3fc08b61df3837701fd6665c1b2b3df7ca44225b.tar.xz kernel-qcow2-linux-3fc08b61df3837701fd6665c1b2b3df7ca44225b.zip | |
drm/amdgpu/gfx9: programing wptr_poll_addr register
Required for SR-IOV.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index e0a3cdc6e759..4c1c5b50cbdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1502,7 +1502,7 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) struct amdgpu_ring *ring; u32 tmp; u32 rb_bufsz; - u64 rb_addr, rptr_addr; + u64 rb_addr, rptr_addr, wptr_gpu_addr; /* Set the write pointer delay */ WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0); @@ -1530,6 +1530,10 @@ static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr)); WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); + wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr)); + WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr)); + mdelay(1); WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp); |