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| author | Leo Liu | 2017-02-15 16:16:25 +0100 |
|---|---|---|
| committer | Alex Deucher | 2017-05-24 23:41:39 +0200 |
| commit | 3639f7d855746406c1c1df81560b4d1d83e8c5a4 (patch) | |
| tree | 551498a63fdf8273260d8e4003b5e7623a3aaed4 /drivers/gpu/drm/amd/amdgpu | |
| parent | drm/amdgpu: add vcn ip block to soc15 (diff) | |
| download | kernel-qcow2-linux-3639f7d855746406c1c1df81560b4d1d83e8c5a4.tar.gz kernel-qcow2-linux-3639f7d855746406c1c1df81560b4d1d83e8c5a4.tar.xz kernel-qcow2-linux-3639f7d855746406c1c1df81560b4d1d83e8c5a4.zip | |
drm/amdgpu: change vcn dec rb command specific for decode
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 12 |
2 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 5dbc6aa33917..550656891a8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -30,12 +30,12 @@ #define AMDGPU_VCN_FIRMWARE_OFFSET 256 #define AMDGPU_VCN_MAX_ENC_RINGS 3 -#define VCN_CMD_FENCE 0x00000000 -#define VCN_CMD_TRAP 0x00000001 -#define VCN_CMD_WRITE_REG 0x00000004 -#define VCN_CMD_REG_READ_COND_WAIT 0x00000006 -#define VCN_CMD_PACKET_START 0x0000000a -#define VCN_CMD_PACKET_END 0x0000000b +#define VCN_DEC_CMD_FENCE 0x00000000 +#define VCN_DEC_CMD_TRAP 0x00000001 +#define VCN_DEC_CMD_WRITE_REG 0x00000004 +#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 +#define VCN_DEC_CMD_PACKET_START 0x0000000a +#define VCN_DEC_CMD_PACKET_END 0x0000000b struct amdgpu_vcn { struct amdgpu_bo *vcpu_bo; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index ee27c79ea236..2e650685e35a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -500,7 +500,7 @@ static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, VCN_CMD_PACKET_START << 1); + amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); } /** @@ -514,7 +514,7 @@ static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) { amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, VCN_CMD_PACKET_END << 1); + amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); } /** @@ -541,7 +541,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, VCN_CMD_FENCE << 1); + amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); @@ -551,7 +551,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, VCN_CMD_TRAP << 1); + amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); } /** @@ -605,7 +605,7 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, amdgpu_ring_write(ring, data1); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1); + amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); } static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, @@ -622,7 +622,7 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_write(ring, mask); amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); - amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1); + amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); } static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, |