diff options
| author | Eric Yang | 2017-07-05 21:30:18 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-09-27 00:08:40 +0200 |
| commit | 133e8e1b35c7772f4903d367035e33e02becbb2d (patch) | |
| tree | 3432bb467aa5d2d510d50f9d8e58eb932257bd4e /drivers/gpu/drm/amd/display/dc/calcs | |
| parent | drm/amd/display: block modes that require read bw greater than 30% (diff) | |
| download | kernel-qcow2-linux-133e8e1b35c7772f4903d367035e33e02becbb2d.tar.gz kernel-qcow2-linux-133e8e1b35c7772f4903d367035e33e02becbb2d.tar.xz kernel-qcow2-linux-133e8e1b35c7772f4903d367035e33e02becbb2d.zip | |
drm/amd/display: Change how we disable pipe split
Before this change, pipe split was disabled by bumping up dpp clock
bounding box for DPM level 0 and 1, this allows validation to pass
without splitting at a lower DPM level. This change reverts this
and instead lowers display clock at DPM level 0, this forces
configurations that need pipe split at DPM level 0 to go to
DPM level 1, where they can be driven without split.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/calcs')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 24f8c4496a61..3118c248409f 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -822,8 +822,7 @@ bool dcn_validate_bandwidth( v->phyclk_per_state[0] = v->phyclkv_min0p65; if (dc->public.debug.disable_pipe_split) { - v->max_dppclk[1] = v->max_dppclk_vnom0p8; - v->max_dppclk[0] = v->max_dppclk_vnom0p8; + v->max_dispclk[0] = v->max_dppclk_vmin0p65; } if (v->voltage_override == dcn_bw_v_max0p9) { |