diff options
| author | Charlene Liu | 2017-07-31 21:35:01 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-09-27 00:16:12 +0200 |
| commit | 6dd28867b1f964226c1c0b1600ecbfa4f8f98bba (patch) | |
| tree | b619cfed5be245b143b3d93e76e36c99bfd47465 /drivers/gpu/drm/amd/display/dc/calcs | |
| parent | drm/amd/display: Move encoder_info_frame to stream_res (diff) | |
| download | kernel-qcow2-linux-6dd28867b1f964226c1c0b1600ecbfa4f8f98bba.tar.gz kernel-qcow2-linux-6dd28867b1f964226c1c0b1600ecbfa4f8f98bba.tar.xz kernel-qcow2-linux-6dd28867b1f964226c1c0b1600ecbfa4f8f98bba.zip | |
drm/amd/display: fix PHYCLK in formula.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/calcs')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 28 |
2 files changed, 27 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c index fb5d8db33a82..e8086c09eb6f 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c @@ -266,6 +266,17 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) v->required_output_bw = v->pixel_clock[k] * 3.0; } if (v->output[k] == dcn_bw_hdmi) { + v->required_phyclk[k] = v->required_output_bw; + switch (v->output_deep_color[k]) { + case dcn_bw_encoder_10bpc: + v->required_phyclk[k] = v->required_phyclk[k] * 5.0 / 4; + break; + case dcn_bw_encoder_12bpc: + v->required_phyclk[k] = v->required_phyclk[k] * 3.0 / 2; + break; + default: + break; + } v->required_phyclk[k] = v->required_output_bw / 3.0; } else if (v->output[k] == dcn_bw_dp) { diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 1922c13d6f22..13b7d8872f97 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -856,18 +856,6 @@ bool dcn_validate_bandwidth( - pipe->stream->timing.v_front_porch; v->vactive[input_idx] = pipe->stream->timing.v_addressable; v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f; - if (pipe->stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { - switch (pipe->stream->timing.display_color_depth) { - case COLOR_DEPTH_101010: - v->pixel_clock[input_idx] = (v->pixel_clock[input_idx] * 30) / 24; - break; - case COLOR_DEPTH_121212: - v->pixel_clock[input_idx] = (v->pixel_clock[input_idx] * 36) / 24; - break; - default: - break; - } - } if (!pipe->plane_state) { v->dcc_enable[input_idx] = dcn_bw_yes; @@ -938,6 +926,22 @@ bool dcn_validate_bandwidth( PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444; v->output[input_idx] = pipe->stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp; + v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc; + if (v->output[input_idx] == dcn_bw_hdmi) { + switch (pipe->stream->timing.display_color_depth) { + case COLOR_DEPTH_101010: + v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc; + break; + case COLOR_DEPTH_121212: + v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc; + break; + case COLOR_DEPTH_161616: + v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc; + break; + default: + break; + } + } input_idx++; } |